Eduard Cerny

Bachir Berkane

Pierre Girodias

Karim Khordoc

Presents a description methodology inspired by timing diagrams and process algebras, so-called hierarchical annotated action diagrams (HAAD). This method is suitable for specifying systems with complex interface behaviors that govern global system behavior. Shows the intuitive meaning of this method, provides formal semantics, and shows how the method can be used for verifying certain aspects of system design. Describes how the HAAD specification can be translated to a VHDL process, and gives a complete example of interfacing ARM7 and a static RAM. Of interest to those involved in defining methods and tools for system-level design specification and verification. Annotation copyrighted by Book News, Inc., Portland, OR

An Interface-Oriented Specification and Verification Method

Hierarchical Annotated Action Diagrams

Carlos Delgado Kloos

In the past few decades Computer Hardware Description Languages (CHDLs) have been a rapidly expanding subject area due to a number of factors, including the advancing complexity of digital electronics, the increasing prevalence of generic and programmable components of software-hardware and the migration of VLSI design to high level synthesis based on HDLs. Currently the subject has reached the consolidation phase in which languages and standards are being increasingly used, at the same time as the scope is being broadened to additional application areas. This book presents the latest developments in this area and provides a forum from which readers can learn from the past and look forward to what the future holds.

Specification, modelling, verification and synthesis of microelectronic systems

Hardware Description Languages and their Applications

Surrendra Dudani

John Havlicek

Dmitry Korchemny

This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012. System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.

SVA: The Power of Assertions in SystemVerilog

Eduard Cerny

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